Google researchers may have solved a crucial bottleneck in microprocessor design, by turning to AI to shrink a laborious design task that used to take months into mere hours. The reinforcement learning technique can enable the co-design of AI hardware, allowing Google to leverage AI technology to design AI chips.
Automating chip design
The details were outlined in a paper published last week in the journal Nature, which detailed research work co-led by Google research scientists Azalia Mirhoseini and Anna Goldie. At stake is a process known as chip floorplanning, which the authors say is a challenge that long defied automation.
Computer chips typically consist of dozens of individual modules from memory subsystems to compute units. Chip floorplanning involves the placement of these components – known as a netlist – onto a two-dimensional grid and ensuring that they are correctly wired while adhering to a variety of conditions. This can range from power consumption, timing, wire length, or area to meet hard constraints on density and routing congestion.
Unfortunately, the exponential growth in chip complexity has rendered many existing methods designed to get this done quickly “largely unusable” on modern chips. Human physical designers typically iterate for months, generating a manual placement and using commercial electronic design automation (EDA) tools that take up to 72 hours to evaluate each placement. The result is months of work.
The team successfully designed a neural architecture to accurately assess a variety of netlists and their placements. This architecture was then used as the encoder of policy and value networks to enable transfer learning. According to the team, the new method generates chip floorplans that are “superior or comparable” to those produced by humans in under six hours.
“In our experiments, we show that, as our agent is exposed to a greater volume and variety of chips, it becomes both faster and better at generating optimized placements for new chip blocks, bringing us closer to a future in which chip designers are assisted by artificial agents with vast chip placement experience,” they wrote.
Aside from significantly speeding up chip floorplanning, the new approach could make it possible to optimize microprocessor designs at earlier stages of the chip design process for better performance. Moreover, it might also allow optimization of chip architectures at the macro scale, and potentially even “facilitate full automation of the chip design process”.
The method is currently used to design the next generation of Google’s AI chips. The paper titled “A graph placement methodology for fast chip design” can be accessed here (pdf).
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